As memory systems have higher capacities, fine fabrications of memory cells, increases in the number of storage bits per cell, and achievements of memory cell arrays with three-dimensional structures have been developed. In a memory system, however, the larger the capacity, the easier the errors occur in stored data. Thus, many memory systems with an on-chip ECC (Error Correcting Code) system have been proposed (for example, Patent Document 1: JP 2009-181439A). The ECC system treats random bit errors (hereinafter simply referred to as “random errors”). In this case, it can support such random bit errors that arise in data writing and so forth. In high-density, three-dimensionally structured memory cells, in addition to such random bit errors, bit errors may arise intensively in a certain region (hereinafter referred to as “burst errors”) due to defects caused on production. The above-described ECC system cannot support such burst errors. Several other on-chip ECC systems have been proposed (Patent Document 2: WO 2008-099723, for example). It is difficult, though, to say that these on-chip ECC systems can support both random errors and burst errors sufficiently.